The present invention relates to a semiconductor integrated circuit device and more particularly to a technique effectively applicable to a semiconductor integrated circuit device having a function device including a cell array which comprises a plurality of standard cells.
Heretofore, in designing the layout of a semiconductor integrated circuit device, diffusion layers for power supply are extended in one direction and a MOS transistor which constitutes a desired circuit is disposed between the diffusion layers. This arrangement is recognized as a cell. An example of layout of such a cell is described, for example, in Japanese Unexamined Patent Publication No. 2006-253375 (Patent Literature 1). The diffusion layers for power supply formed to extend in one direction are each sometimes called “tap.”
Reference is also made here to Japanese Unexamined Patent Publication No. 2006-228982 (Patent Literature 2). According to the technique disclosed therein, in a semiconductor integrated circuit including a plurality of standard cells having diffusion layers for forming circuits, the diffusion layers for circuit in the standard cells adjacent to each other are arranged at a predetermined diffusion layer spacing, and in the case where the diffusion layers for circuit are formed at mutually different phases by phase shift, there are discontinuously formed diffusion layers for tap to draw a power-supply potential or a ground potential in the vicinity of the adjacent diffusion layers for circuit. By so doing, patterns are highly integrated without lowering the resolution of the patterns and without causing any such problem as phase contradiction.
[Patent Literature 1]
Japanese Unexamined Patent Publication No. 2006-253375
[Patent Literature 2]
Japanese Unexamined Patent Publication No. 2006-228982